基于fpga的多功能数字时钟 在数码管显示
verilog语言编写 可实现校时 暂停以及设定闹钟的功能
FPGA time clock (2015-05-02, VHDL, 74KB, 下载4次)
采用可综合的Verilog代码编写一个带闹钟功能的数字钟。使其具有以下功能：
1)计时功能：包括小时、分钟、秒钟。
2)校时功能：对小时、分钟和秒钟进行手动校时。
3)定时和闹钟功能：能在手工设定的时间产生闹铃音。
Using synthesizable Verilog coding a digital clock with alarm. It has the following features:
1) timing functions include: hours, minutes, seconds.
2) When the school functions: hours, minutes and seconds to the manual correction.
3) timing and alarm functions: to produce an alarm sound at the set time manually. (2015-01-24, VHDL, 2KB, 下载8次)
这个程序是基于Quartus II的，能通过数码管显示时、分、秒，具有闹钟的功能，能通过按键校时。
his program is based on the Quartus II, and when through digital display hours, minutes, seconds, and has an alarm clock function, button through school. (2014-11-30, VHDL, 1KB, 下载4次)
本设计选用 ALTERA 公司的 EP1C12Q240C8 芯片，利用 VHDL 语言采用自
顶向下的方法在 Quartus Ⅱ环境下完成了数字钟的设计，最后在实验箱上进行测
试。该数字钟包含的功能有计时、显示星期、校时校分、清零、整点报时、音乐
闹铃。
The design uses the silicon chip EP1C12Q240C8 produced by the company of
ALTERA. And with the help of VHDL, the design of a digital clock is completed
using the top-down approach under Quartus Ⅱ, finally carried out in the SmartSOPC.
Functions of the digital clock are: timer, showing day, setting time, resetting, Chime
on every hour, and alarm with music. (2014-05-20, VHDL, 226KB, 下载4次)
数字钟的设计，系统分为5个模块，Freq_div模块，Clock_cnt模块，Clock_ctl模块，Key_ctl模块和Display模块。系统目标：用8个LED 显示时间，如9点25分10秒显示为，09－25－10。（2）设置2个按键，按键SET用于工作模式选择，按键UP用于校时。
Digital clock design, the system is divided into five modules, Freq_div module, Clock_cnt module, Clock_ctl module, Key_ctl module and Display Module. System goal: 8 LED display time as 9:25:10 displayed as ,09-25-10. (2) Set two buttons SET button for mode selection button when UP for school. (2014-03-28, Others, 1561KB, 下载2次)
数字钟，校时较分，显示,用元件例化写的vhdl文件，两个24进制，1个60进制计数器
Digital clock, when the school over the points, show cases with elements of writing vhdl file, two 24-band, a 60-ary counter (2014-03-03, VHDL, 457KB, 下载2次)
DLP Discovery 4100
数字微镜(DMD)空间光开关光调制器开发系统
1.全面兼容德州仪器TI DLP D4100 开发系统. 能够支持1920X1080 DMD(DMD微镜为10.6微米,本征分辨率为1920X1080)
数字微镜(DMD)空间光开关光调制器开发系统
2. 1024 X 768 的DMD(4:3)有两种微镜结构，一种是13.68 微米，
对角线长度为0.7 英寸；另一种是10.8 微米的，对角线长度为0.55
英寸；我们系统都能支持所有主流分辨率DMD
3. 支持USB2.0 高速度传输图片和控制信号
4. 开放式控制软件基于Windows XP 全速度USB驱动,在Visual
Basic 下编制,开发式接口, 易于高精度光学科研实验
5. 提供丰富的Windows XP 的USB 控制程序和API 开发系统
6. 支持XGA, 1080p 和1920x1200 分辨率单个微镜精确控制
7. 开放式FPGA 架构, 提供示例FPGA 的二次开发选择和客户
定制功能
8. 高速二进和任意灰度制图片显示 输入输出系统触发,支持通
用客户顶GPIO 口设置.
9. 我们能为客户提供全程独特定做和设计服务.
应用:
结构光投影,激光全息,无掩模光刻,高光谱成像,激光光束校形,
3D 测量和3D 打印机技术, 光谱分析.
Jefferson_zhao@163.com
DLP DMD Discovery 4100 (2014-01-20, Visual Basic, 6299KB, 下载31次)
verilog电子时钟，可以实现复位、计时、校时、闹钟等多种功能。
verilog electronic clock, you can achieve a variety of functions reset, time, school, alarm clock and so on. (2013-12-12, VHDL, 363KB, 下载5次)
数字钟，实现整点报时以及校时功能，烟大数字逻辑课程实验。
Digital clock, realize the whole point timekeeping and school function, smoke large digital logic course experiment. (2013-11-08, VHDL, 496KB, 下载3次)
数字钟，功能：12时/24时切换显示，校时,时间很准（4位数码管显示），内含sof，pof，tcl，四个文件，在开发板C1上已实现
digital clock ，verilog (2013-08-21, VHDL, 18KB, 下载7次)
多功能数字电子表
（１）正常计时：秒（60）、分（60）、小时（24）计数；秒计时的频率为1Hz，数码管用动态扫描实时显示计时的小时、分、秒。
（２）整点报时：逢整点蜂鸣器在“59”分钟的第51、53、55、57秒发频率为512Hz的低音，在“59”分钟的第59秒发频率为1024Hz的高音。
（３）校时：
校小时, 显示小时数码管以4Hz的频率递增计数；
校分, 显示分数码管以4Hz的频率递增计数；
校秒, 秒清0。
其他：
1．晶振为12 MHz
2. 采用CPLD 器件为ALTERA 的EPM7064SL-44
3．采用数码管显示
Multifunction digital electronic watch (1) normal time: second (60), points (60), hours (24) counts second timing frequency of 1Hz, dynamic scanning real-time display of digital works timekeeping hour, minutes and seconds. (2) The whole point timekeeping: Every whole point of the buzzer in the " 59" minutes of 51,53,55,57 second frequency is 512Hz bass made in the " 59" minutes of the first 59 seconds made the treble frequency is 1024Hz . (3) school: school hours, hours of digital tube display frequency of 4Hz counts school hours, the display of digital 4Hz for counting school, seconds cleared. Others: 1. Crystal is 12 MHz 2. Using ALTERA CPLD device as the EPM7064SL-44 3. Using digital display (2013-08-20, VHDL, 503KB, 下载3次)
基于QuartusII开发环境，Cyclone III开发板的VerilogHDL多功能数字钟程序。可实现24小时计时，手动校时，闹钟，整点报时功能。分频模块在仿真和烧写是需要改变。
QuartusII based development environment, Cyclone III development board VerilogHDL multifunction digital clock procedures. Can achieve 24-hour clock, manual timing, alarm, hourly chime functions. Frequency module in the simulation and programming needs to change. (2013-07-24, VHDL, 1895KB, 下载4次)
数字时钟6位数码管显示。主要器件为74ls48和74ls160 /74ls161。功能：1.显示时、分、秒。2. 可以24小时制或12小时制。3. 具有校时功能
Digital clock six digital tube display. Main components of 74ls48 and 74ls160/74ls161. Features: 1. Shows hours, minutes, seconds. (2) a 24-hour or 12-hour clock. 3 a school function (2013-07-18, Others, 490KB, 下载7次)
多功能数字钟，具有年月日时分秒功能，同时能校时，1个八段数码管显示
Multifunctional digital clock with date, hour function, and can school, an eight digital tube display (2013-07-10, DOS, 763KB, 下载3次)
美国名校的嵌入式课程讲义，多核cpu、内存、vliw指令等方面的设计原理
U.S. elite embedded lecture notes, multicore cpu, memory, vliw instruction and other aspects of design principles (2013-07-07, C/C++, 136KB, 下载6次)
数字电子钟的设计，振荡器产生稳定的高频脉冲信号,作为数字钟的时间基准,然后经过分频器输出标准秒脉冲。秒计数器满60后向分计数器进位,分计数器满60后向小时计数器进位,小时计数器按照“24翻1”规律计数。计数器的输出分别经译码器送显示器显示。计时出现误差时,可以用校时电路校时、校分。
Digital electronic clock design, stable high frequency oscillator generates a pulse signal as a digital clock time reference, and then passes through a divider output standard second pulse. Second counter at least 60 minutes after the binary counter, minute counter at least 60 hours after the binary counter, hour counter in accordance with the "24 turn a" regular count. The outputs of the counter is sent to the decoded display. Timing errors, you can use the circuit when the school when the school, school hours.
(2013-07-02, VHDL, 1469KB, 下载1次)
设计一台能显示时、分、秒的数字电子钟，具体要求如下：
（1）时计数器用24进制计时电路，分、秒计数器用60进制计分、计秒电路；
（2）可手动校时，能分别进行时、分的校正；
（3）能实现整点报时功能。
Design a table can display hours, minutes and seconds of digital electronic clock, the specific requirements are as follows: (a) when the counter with 24 hexadecimal timing circuits, minutes, seconds counter with 60 decimal points, namely, second circuit (2) may be Manually school, be able to separate hours, minutes correction (3) to achieve the whole point timekeeping function. (2013-06-23, VHDL, 913KB, 下载3次)
电子时钟设计 包含校时和闹钟功能 闹钟播放一段音乐 ppt和word报告也有 太大不上传 需要的发邮箱lin170587788@gmail.com
Electronic clock and alarm functions including school play a musical alarm clock ppt and word report also does not upload much needed hair mailbox lin170587788@gmail.com (2013-06-17, VHDL, 315KB, 下载4次)
用 Verilog HDL 设计一个多功能数字钟，包含以下主要功能：
1） 计时，时间以 24 小时制显示；
2） 校时；
3） 闹钟：设定闹钟时间，可利用 LED 闪烁作为闹钟提示；
4） 跑表：启动、停止；
5） 其他。
Using Verilog HDL design a multi-functional digital clock contains the following main functions: 1) time, the time is displayed in 24-hour clock 2) school 3) Alarm Clock: Set the alarm time, you can use the LED flashes as an alarm 4) Stopwatch: start, stop 5) Other. (2013-04-24, VHDL, 1206KB, 下载33次)
设计一个多功能数字时钟:时钟显示，手动校时，整点报时，闹钟功能
Clock manually school, the whole point timekeeping, alarm clock function (2013-04-09, VHDL, 360KB, 下载8次)