合肥工业大学合肥校区(HFUT)计算机科学与技术专业(CS)。本仓库存有大一至大三的实验+课设及其源码,有疑问可以邮箱联系(回复时间不一定)。欢迎Star,会不定时更新
Computer Science and Technology (CS) at Hefei Campus of Hefei University of Technology (HFUT). This warehouse has the experiment+curriculum and its source code from freshman to junior. If you have any questions, you can contact us by email (the reply time is uncertain). Welcome Star, it will be updated irregularly (2024-01-21, Rich Text Format, 0KB, 下载0次)
UFSC语言和硬件描述课程知识库，Araranguá校区。，
Repository for the Language and Hardware Description course at UFSC, Araranguá campus., (2023-03-02, VHDL, 0KB, 下载0次)
实现计时，置数，闹钟设置，切换显示等
1.硬件资源：FPGA开发板一块，电源线一根，下载器一个
2.开发板用到的资源：三颗独立按键，一位拨码开关，八位七段数码显示器，
蜂鸣器
3.功能设计：时钟功能，校时功能，闹钟功能
整个系统分为7大模块
Realize timing, setting, alarm setting, switching display, etc
1. Hardware resources: one FPGA development board, one power cord and one Downloader
2. Resources used in the development board: three independent buttons, one dial switch, eight seven segment digital display,
Buzzer
3. Function design: clock function, timing function, alarm function
The whole system is divided into seven modules (2020-06-16, Verilog, 2381KB, 下载0次)
程序是实现一个数字钟，有进位、清零、校时与校分功能。数字钟的分钟和小时是用数码管显示
COUNTER AND ALARMProblem C. Cave Escape Google Kickstart Round G 2018 [Small Input] (2019-04-26, Verilog, 1599KB, 下载1次)
实现一个24小时制的数字时钟，可切换校时模式，带有闹钟和整点报时功能，约束文件基于basys2实验板
A 24-hour digital clock with alarm clock and full-time alarm function can be switched. The constraint file is based on the basys2 experimental board. (2018-12-30, Verilog, 36571KB, 下载3次)
基于VHDL的数字时钟课程设计，可实现校时、计时已经闹钟功能。
The course design of digital clock based on VHDL can realize the alarm clock function of school hour and time. (2018-12-25, VHDL, 186KB, 下载5次)
设计了一个电子时钟，功能包括定点报时，设置闹钟，校时等
Designed an electronic clock, features include fixed-point timekeeping, setting alarms, school hours, etc. (2018-07-01, Quartus II, 8987KB, 下载2次)
12制 24制可切换电子钟，有时分秒，都可校时
clock can adjust minute,hour,seconds (2018-05-11, Verilog, 747KB, 下载1次)
自己用verilog HDL写的一个数字钟模块，包括校时功能，在Maxplusii下调试和下载通过
A digital clock module written by Verilog HDL, including timing function, debugging and downloading through Maxplusii. (2018-04-13, Verilog, 3KB, 下载2次)
多功能数字种 可实现校时 闹钟 整点报时等功能
Multi-function digital species can realize the function of time alarm clock and other functions (2018-02-10, Verilog, 2KB, 下载2次)
自己开发的电子时钟小程序，通过数码管显示时间，key1和key2控制校时校分，key3切换时钟模式和闹钟模式，切换到闹钟模式再按key1和key2即可设定闹钟时间。key4控制开启/关闭闹钟。有整点报时功能。
Self developed electronic clock applet, through the digital tube display time, key1 and key2 control time correction, Key3 switch clock mode and alarm mode, switch to the alarm mode, then press key1 and key2 can set the alarm time. Key4 controls the opening / closing of the alarm clock. There is a whole time function. (2017-12-06, Verilog, 9120KB, 下载2次)
基于verilog简单数字时钟程序，可实现校时，校分功能
Based verilog simple digital clock procedures, can be achieved when the school, school division function (2016-07-03, VHDL, 1128KB, 下载1次)
基于FPGA的数字万年历设计。可显示年月日时分秒星期，可校时，可整点报时。
FPGA-based design of digital calendar. Displays the date when the minutes and seconds the week, when the school can be the whole point timekeeping. (2016-06-27, VHDL, 150KB, 下载8次)
数字时钟，实现24小时数码管显示，可以实现按键校时
Digital clock, 24 hours to achieve digital display, you can achieve the key school (2016-06-17, VHDL, 1789KB, 下载2次)
数字钟；可以实现校时、走时、单独计时以及闹钟功能。
Digital clock can be achieved when the school, while walking alone timekeeping and alarm function. (2016-05-21, VHDL, 432KB, 下载2次)
该程序主要是用Verilog HDL语言编写的多功能数字钟，包括校时，调试，整点报时和万年历模块。
The program is mainly used Verilog HDL language multifunction digital clock, including at school, debugging, the whole point timekeeping and calendar modules. (2016-05-14, VHDL, 9KB, 下载5次)
基于basys2的简易数字钟，包含校时功能
A simple digital clock base on basys2 board, including timing function. (2016-05-13, Others, 414KB, 下载11次)
显示时、分、秒，有手动校时功能，计时过程具有报时功能
Display hours, minutes, seconds, manual timing function, timing processes with chime (2016-03-26, VHDL, 13KB, 下载1次)
信号定义： clk： 标准时钟信号，本例中，其频率为4Hz； clk_1k： 产生闹铃音、报时音的时钟信号，本例中其频率为1024Hz； mode： 功能控制信号； 为0：计时功能； 为1：闹钟功能； 为2：手动校时功能； turn： 接按键，在手动校时功能时，选择是调整小时，还是分钟； 若长时间按住该键，还可使秒信号清零，用于精确调时； change： 接按键，手动调整时，每按一次，计数器加1； 如果长按，则连续快速加1，用于快速调时和定时； hour,min,sec：此三信号分别输出并显示时、分、秒信号， 皆采用BCD码计数，分别驱动6个数码管显示时间； alert： 输出到扬声器的信号，用于产生闹铃音和报时音； 闹铃音为持续20秒的急促的“嘀嘀嘀”音，若按住“change”键， 则可屏蔽该音；整点报时音为“嘀嘀嘀嘀—嘟”四短一长音； LD_alert： 接发光二极管，指示是否设置了闹钟功能； LD_hour： 接发光二极管，指示当前调整的是小时信号； LD_min： 接发光二极管，指示当前调整的是分钟信号。
Signal definition: clk: standard clock signal, in this case, the frequency of 4Hz clk_1k: generating an alarm sound, the sound of the chime of the clock signal, in this case a frequency of 1024Hz mode: function control signal to 0: timing functions 1: alarm clock function 2: Manual calibration function turn: take the keys, function in the manual when school choice is to adjust the hours, or minutes if long press the button, but also to second signal cleared for precise time-setting change: access key, manually adjust the time, every time you press, the counter is incremented if long press, then in quick succession by 1, when used to quickly tune and timing hour, min, sec: The three signals are output and display hours, minutes, seconds signal using BCD code are counted separately driven six digital tube display time alert: a signal output to the speaker for generating an alarm tone chime tone alarm tone sustained 20 seconds of rapid " Didi tick" sound, if the hol (2015-12-09, VHDL, 16KB, 下载2次)
这是本人在学校做的一个DDS信号发生器，频率相位可调。输入时钟50Mhz
DDS phase frequency adjustable Verilog (2015-07-29, VHDL, 2380KB, 下载22次)