可实现校时，仿电台报时，闹钟，报整点时数
The school can be realized when the fake radio timekeeping, alarm clock, reported that the number of hours the whole point of (2009-12-30, VHDL, 13KB, 下载18次)
s1. 所设计数字钟具有“时”、“分”、“秒”的十进制数字显示（小时从00～23）。
2. 可以进行手动校时、校分功能。
3. 能进行整点报时。从59分51秒开始每隔2秒钟连续发出四次低音“嘟。嘟、嘟、嘟”，，最后一次发出高音“嗒”。此信号响起时即达整点。
you can see see (2009-12-03, VHDL, 157KB, 下载24次)
1、24小时计数显示；
2、具有校时功能（时，分） ；
3、实现闹钟功能（定时，闹响）；
1,24 hours counting display 2, with the school when the function (hour, minute) 3 to achieve alarm functions (timing, downtown ring) (2009-12-01, VHDL, 7KB, 下载4次)
基于vhdl的数字钟,分别由6个数码管显示24小时、60分钟、60秒的计数显示；设有校时、校分、秒清零校正功能，分别由3个按键控制；验证可用。
On vhdl digital clock, respectively, by 6 digital tube display 24 hours, 60 minutes, 60 seconds of the count display with school hours, school hours, seconds, cleared correction function, respectively, by three buttons control verification is available. (2009-11-13, VHDL, 261KB, 下载3次)
利用maxplus2完成
1、 完成带时、分、秒显示的24h计时功能；
2、 能完成整点报时功能，要求当数字钟的分和秒计数器计到59min52s时，驱动音响电路，四高一低，最后一声高声结束，整点时间到；
3、 完成对“时”和“分”的校时，并能对秒计数器清零。
Use maxplus2 completed one complete with hours, minutes, seconds, show 24h time functions 2, can complete the whole point timekeeping function, require that when the digital clock minutes, and seconds counter when the count to 59min52s, driver audio circuit, four high and one low, soon as the end of the last loud, the whole point of time to 3 to complete the " time" and " sub" when the school is also able to clear the seconds counter. (2009-11-01, WORD, 165KB, 下载7次)
这时一个关于数字钟的VHDL程序，有计时、校时、报时等功能
When a digital clock on the VHDL program, there is time, school time, timer and other functions (2009-09-22, VHDL, 79KB, 下载6次)
这时一个数字钟的VHDL程序，有计时、校时、整点报时功能，很适合做EDA设计之用
When a digital clock in VHDL procedures, time, school hours, the whole point timekeeping function, it is suitable for use in EDA Design (2009-09-22, VHDL, 1KB, 下载7次)
这时用VHDL语言编写的多功能数字钟，具有正常的计时功能，还能进行校时、校分，并且具有整点报时功能
Then with the VHDL language multi-functional digital clock, with the normal timing functions, but also to the school, the school hours, and have the whole point timekeeping function of (2009-09-22, VHDL, 445KB, 下载13次)
这是一个数字时钟的数字逻辑电路，整个工程打包上传，时钟可以计时、校时、整点报时、定时闹钟。使用电路图实现的。在quatarsII里面仿真的并且下载到DE2板上运行过。
This is a digital clock digital logic circuits, the whole project package upload, the clock could be time, school hours, the whole point timekeeping, timing alarm clock. The use of circuit implementation. The quatarsII inside the simulation, and downloaded to the DE2 board to run-off. (2009-09-15, HTML, 1017KB, 下载20次)
1.计时功能采用24小时方式，显示小时、分钟、秒。
2.采用双键校时法，MODE和SET，前者选择始终模式（包括小时、分、秒校时），后者校时脉冲。
3.结果用6个共阳数码管显示。
1. Time functions the way the 24-hour, show hours, minutes, seconds. 2. The use of double bond at the Law School, MODE and SET, always choose the former model (including the hours, minutes and seconds when the school), the latter pulse school. 3. Results A total of six positive digital display. (2009-07-27, VHDL, 318KB, 下载3次)
用VHDL实现的完整数字钟代码，时分秒计时、校时、整点仿电台报时。
Used to achieve a complete VHDL code digital clock, accurate time at school, the whole point of imitation time radio. (2009-05-21, VHDL, 288KB, 下载5次)
数字钟的VHDL源程序，可以实现校时，校分等功能，并在试验箱上运行成功
The VHDL source code digital clock, you can achieve at school, school grade features, and success in the chamber is running on (2009-04-08, VHDL, 302KB, 下载5次)
数字钟的VHDL源程序，可以实现校时，校分等功能，并在试验箱上运行成功
The VHDL source code digital clock, you can achieve at school, school grade features, and success in the chamber is running on (2009-04-08, VHDL, 303KB, 下载6次)
VHDL的数字时钟程序
24小时计数显示；
具有校时功能（时，分） ；
实现闹钟功能（定时，闹响）；
VHDL digital clock counting procedures showed that 24 hours with a school function (hours, minutes) the realization of an alarm clock function (timing, downtown ring) (2009-01-08, VHDL, 12KB, 下载6次)
VHDL数字钟设计程序
设计要求
基本要求：
1、24小时计数显示；
2、具有校时功能（时，分） ；
附加要求：
1、实现闹钟功能（定时，闹响）；
VHDL digital clock design process design requirements for the basic requirements: 1,24 hours count display 2, with a school function (hours, minutes) additional requirements: 1, the realization of an alarm clock function (timing, downtown ring) (2008-12-23, VHDL, 7KB, 下载129次)
以前学习VHDL语言时做的一个电子闹钟程序，可以实现时，分，秒的计时以及定时，校时，闹钟，整点报时的功能。
VHDL language before learning to do procedures in an electronic alarm clock, you can realize hours, minutes and seconds of time and from time to time, school time, alarm clock, the whole point timekeeping function. (2008-09-25, VHDL, 166KB, 下载13次)
电子时钟 EDA
基本要求：
24小时计数显示；
具有校时功能（时，分）
附加要求
1、秒表功能（复位，计时
Electronic clock EDA basic requirements: a 24-hour count showed with a school function (hours, minutes,) Additional requirement 1, stopwatch functions (reset, clock (2008-09-18, VHDL, 3KB, 下载33次)
ADC0809采样控制电路的实现ADC0809是CMOS的8位A/D转换器，片内有8路模拟开关，可控制8个模拟量中的一个进入转换器中，转换时间约100us。主要控制信号有，START是转换启动信号，高电平有效。ALE是3位通道选择地址（ADDC、ADDB、ADDA）信号的所存信号。当模拟量送至某一输入端（如IN1或IN2），由3位地址信号选择，而地址信号由ALE锁存。
ADC0809频 实 ADC0809CMOS8位A/D 转 片8 模 饪?兀 煽8模 械一 转 校 转 时 约 100us要藕校START 转 藕牛 叩 平效ALE3位 通 选ADDCADDBADDA藕诺藕拧模 某一 耍 IN1IN23位藕选 瘢 藕ALE file (2008-09-04, VHDL, 28KB, 下载38次)
基于bcd码校时的数字钟，带闹钟，正点报时，和日历功能
Price coverlet bcd tungsten cavity时corchorifolius tub callous钟turbulent age钟， ， ，时forlorn Hao Yu Rui Kun Dang 日 Xikui (2008-07-11, VHDL, 2KB, 下载29次)
两个按键控制校时的VHDL时钟源码，带定时闹钟和日历功能
Two buttons control the school at the time of VHDL source clock, alarm clock and calendar with timing function (2008-07-11, VHDL, 2KB, 下载17次)