电子数字钟，周期为24小时，显示满刻度为23时59分59秒，另外还具有校时功能和闹钟功能
Electronic digital clock, 24-hour period, indicating full scale as 23:59:59, when the school also has a function and alarm functions (2011-05-24, VHDL, 44KB, 下载6次)
1) 计时计数器用24进制计时器电路。
2) 可手动校时，能清零及分别进行时、分、秒的校正。
3) 可整点报时，扬声器发出时长为1s的信号。
4) 可设置闹钟功能。当计时计到预定时间时，扬声器发出闹铃信号，可控制闹铃时长。
clock (2010-12-17, VHDL, 844KB, 下载5次)
用Verilog HDL 设计一个多功能数字钟，包含以下主要功能：
（1） 计时，时间以24小时制显示。
（2） 校时，
（3） 跑表：启动、停止、暂停
Verilog HDL design with a multi-functional digital clock, includes the following main functions: (1) time, time to 24-hour display. (2) school, (3) stopwatch: start, stop, pause (2010-12-02, VHDL, 1342KB, 下载7次)
电子钟的设计，(1) 计时功能：这是本计时器设计的基本功能，可进行时、分、秒计时，并显示。
(2) 闹钟功能：如果当前时间与设置的闹钟时间相同，则扬声器发出一段音乐，并维持一分钟。
(3) 调时调分调闹钟功能：当需要校时或者要重新设置闹钟的时间时，可通过实验箱上的按键控制。
The design of electronic clock, (1) timer function: This is the basic design of the timer function, can be hours, minutes, seconds, time, and displayed. (2) Alarm function: If the current time and set the alarm clock the same time, the speaker issued a piece of music, and to maintain a minute. (3) adjusting the tone when the tone alarm sub-functions: the school or when when you need to re-set the alarm time, the experimental box through the keys on the control. (2010-11-30, VHDL, 82KB, 下载7次)
数字钟的VHDL语言实现基本功能，包括
1、24小时计数显示；
2、具有校时功能（时，分） ；
附加要求：
1、实现闹钟功能（定时，闹响）；
Digital clock in the VHDL language for basic functions, including 1,24-hour count display 2, when a school function (hour, minute) additional requirements: 1, to achieve the alarm function (time, alarm sound) (2010-11-25, VHDL, 1KB, 下载3次)
基于CPLD的交通灯控制，完成交通灯的功能，校错能力
CPLD-based control of traffic lights, traffic lights to complete the function, the school was wrong capacity (2010-10-08, VHDL, 426KB, 下载5次)
本文介绍了一个多功能电子钟的设计方案。该方案具有计时、整点报时、校时、校分、闹钟等多项功能。此方案基于Altera 公司的 Cyclone 芯片及Quartus II 7.2 软件。整体设计采用自顶向下的设计思想，大量使用了器件模块化操作。本文对于研究数字钟及扩大其应用，有着非常现实的意义。
This paper describes a multi-clock design. The program has the time, the whole point of time, school hours, school hours, alarm clocks and many other features. This program is based on Altera' s Cyclone chip and Quartus II 7.2 software. The overall design using top-down design, extensive use of modular operation of the device. This digital clock for research and expand its application, has a very practical significance. (2010-09-08, VHDL, 756KB, 下载12次)
数字钟，用VHDL 编写。具有计时，校时（调分调时），报时功能
Digital clock, written with VHDL. With time, school time (when the tone on tones), timekeeping function (2010-09-02, VHDL, 188KB, 下载5次)
B码的产生 使用B码进行校时 用来产生B码
以及B码的格式 说明
B generated code when using the B codes school code used to generate B and B code format description (2010-07-23, VHDL, 332KB, 下载130次)
B码校时（B码的产生）用来产生B码，实现B码校时 使设备进行同步。
B码校时（B码的产生）用来产生B码，实现B码校时 使设备进行同步。 (2010-07-23, VHDL, 5KB, 下载89次)
电子钟（模式转换24/12进制，校时，校分）
Clock (24/12 hex mode conversion, school hours, school hours) (2010-07-09, VHDL, 102KB, 下载2次)
VHDL数字钟设计程序 设计要求 基本要求： 1、24小时计数显示； 2、具有校时功能（时，分） ； 附加要求： 1、实现闹钟功能（定时，闹响）；-
VHDL design process digital clock design basic requirements: 1.24 hours count display 2, when a school function (hour, minute) additional requirements: 1, to achieve alarm (time, alarm sound) - (2010-06-22, VHDL, 70KB, 下载48次)
VerilogHDL编译基本功能具有“秒”、“分”、“时”计时功能，小时按24小时制计时。具有校时功能，能对“分”和“小时”进行调整。扩展功能
仿广播电台正点报时。在59分51秒、53秒、55秒、57秒发出低音512Hz信号，在59分59秒时发出一次高音1024Hz信号，音响持续1秒钟，在1024Hz音响结束时刻为整点。
定时控制，其时间自定；
可任意设定时间的闹钟
自动报整点小时数
小时显示：可切换12小时/24小时显示
VerilogHDL compile the basic functions of a " second" , " division" and " when" time function, hour by 24-hour time. When a school function, can " divide" and " hours" to adjust. Radio extension punctual timekeeping imitation. In 59 minutes and 51 seconds, 53 seconds, 55 seconds, 57 seconds sent the bass 512Hz signal, in 59 minutes and 59 seconds to issue a Treble 1024Hz signal, sound for 1 second, the end of the 1024Hz sound time for the whole point. Timing control, its time to custom can be arbitrarily set the time automatically report the whole point of the alarm clock an hour for several hours show: switchable 12 hours/24 hours display (2010-06-20, VHDL, 1KB, 下载5次)
实验利借助于Quartus II 软件设计了一个多功能数字钟，实现了校时，校分，清零，保持和整点报时等多种基本功能，此外还实现了闹钟，星期，音乐闹铃等附加功能。本文首先利用Quartus II进行原理图设计并仿真调试，最后在实验板上验证了设计的正确性。
关键字：数字钟 闹钟 仿真 准点报时
Quartus II software by means of experimental Lee designed a multi-functional digital clock and realized the school, the school hours, cleared, and the whole point of time keeping and other basic functions, in addition to achieve the alarm clock, week, music, alarm, etc. Additional function. This paper carried out using Quartus II schematic design and simulation debugging, and finally verified in the experimental board design is correct. Keywords: digital clock alarm clock simulation of quasi-point of time (2010-05-08, VHDL, 1158KB, 下载13次)
闹钟、电子钟典型实例，具有校时，整点报时等功能
Alarm clock, electronic clock typical example, a school, the whole point of time and other functions (2010-04-25, VHDL, 245KB, 下载7次)
多功能数字时钟课程设计可用的,含手动校时电路，整点报时电路。报时长短需要自己设置程序
digital clock decode (2010-04-24, VHDL, 1KB, 下载9次)
eda实验时钟电路系统由秒时钟产生电路、走时电路模块、数字显示模块、校时模块、语音报时模块、工业控制模块
eda test clock circuit generated by the second clock circuit, the circuit blocks away, the digital display module, the campus module, voice timekeeping module, industrial control modules (2010-04-18, VHDL, 2578KB, 下载27次)
基于FPGA的数字电子钟设计，系统总程序由分频模块、“时分秒”计数器模块、数据选择模块、报时模块、动态扫描显示和译码模块组成。得到一个将“时”、“分”、“秒”显示于人的视觉器官的计时装置。它的计时周期为24小时，显示满刻度为23时59分59秒，另外有校时、校分和整点报时功能，并通过数码管驱动电路显示计时结果。
FPGA-based design of digital electronic clock, the system program by the total frequency module, " the minutes and seconds" counter module, data selection module, timer module, dynamic scanning display and decoding module. Get a will " ," and " division" and " seconds" display on the human visual organ of the timing device. It' s time for the 24-hour period, indicating full scale as 23:59:59, and another school, the school hours and the whole hour, and through digital tube display driver circuit timing results. (2010-04-07, VHDL, 62KB, 下载27次)
这是一个基于FPGA设计的24时多功能数字钟，具有正常星期、时、分、秒计时，动态显示，保持、清零、快速校分、整点报时、闹钟功能。
This is an FPGA-based design of multi-function digital clock 24 hours, with a normal week, hours, minutes, seconds, timing, dynamic display, maintaining, resetting, fast school hours, the whole point timekeeping, alarm clock function. (2010-03-06, VHDL, 773KB, 下载27次)
多功能数字钟实现闹铃，整点报时，校时，仿广播电台报时功能
multifuntional digital clock written in verilog (2010-02-12, VHDL, 1KB, 下载7次)