verilog写的时钟程序，带有校时和闹铃功能
clock program written with verilog (2012-02-25, VHDL, 2KB, 下载7次)
数字钟的电路图.1.显示时、分、秒。2. 可以24小时制或12小时制。3. 具有校时功能，可以对小时和分单独校时，对分校时的时候，停止分向小时进位。校时时钟源可以手动输入或借用电路中的时钟。4. 具有正点报时功能，正点前10秒开始，蜂鸣器1秒响1秒停地响5次。
Digital clock circuit diagram (2012-02-21, VHDL, 943KB, 下载5次)
用VHDL语言编写数字钟的程序，实现数字钟的完整功能，如计时、校时、闹钟和整点报时
Digital clock using VHDL language programs, digital clock several functions, such as timing, timing, alarm and hourly chime (2012-01-08, Others, 386KB, 下载5次)
用VHDL语言编写数字钟的程序，实现数字钟的几个功能，如计时、校时、闹钟和整点报时
Digital clock using VHDL language programs, digital clock several functions, such as timing, timing, alarm and hourly chime (2012-01-08, Others, 2KB, 下载4次)
多功能数字钟 24小时计时 整点报时功能 闹钟设置功能 校时 复位等
Multi-function digital clock 24 hours to strike the alarm clock on the hour function when the reset function, etc (2012-01-05, VHDL, 2KB, 下载6次)
多功能数字钟 24小时计时 整点报时功能 闹钟设置功能 校时 复位等
Multi-function digital clock 24 hours to strike the alarm clock on the hour function when the reset function, etc (2012-01-05, VHDL, 11KB, 下载7次)
数字时钟，整点报时，有校分校时功能，底层用VHDL，顶层原理图
Digital clock, the whole point of time, when a school campus functions, the bottom with VHDL, top-level schematic (2012-01-05, VHDL, 4KB, 下载4次)
基于VHDL基于VHDL数字电子钟设计（时、分、秒），有校时，分频，倒计时流水灯灯功能。
Based on VHDL VHDL-based design of digital electronic clock (hours, minutes, seconds), there is the school, the frequency, the countdown water lights lamp function. (2012-01-04, VHDL, 2KB, 下载3次)
满足数字钟的一切功能，包括定时，整点报时，时分秒的校时，年月的显示
Digital clock to meet all of the features, including timing, the whole point of time, when every minute of school, the years of the show (2011-12-18, VHDL, 265KB, 下载3次)
电子表的设计,包括正常计时模块，LED显示模块，定时报警模块，校时模块，秒表模块。
Electronic form design, including the normal timing module, LED display module, timing alarm module, timing modules, stopwatch modules. (2011-12-14, VHDL, 2KB, 下载7次)
此数字钟具有时，分，秒计时并显示功能；
2.能进行24/12小时制计时模块的切换；
3.具有校时，清除功能，能对时，分，秒进行调整；
4.具有整点报时功能：在59分51秒，59分53秒，59分55秒，59分57秒发出低音256HZ信号，在59分59秒发出一次高音1024HZ信号，音响持续一秒钟，在1024HZ音响结束时刻即为整点；
This digital clock with hours, minutes, seconds, chronograph and display 2 24/12 hour time capable of switching modules 3 with the school, clean up, can the hours, minutes, seconds to adjust 4 with The whole point timekeeping functions: in 59 minutes and 51 seconds, 59 minutes and 53 seconds, 59 minutes and 55 seconds, 59 minutes and 57 seconds bass 256HZ signal sent in 59 minutes and 59 seconds to issue a treble 1024HZ signals, sound for one second, sound in 1024HZ end time is the whole point (2011-11-13, VHDL, 703KB, 下载4次)
多功能数字钟，实现了计时、校分、闹钟、日历等功能，已通过仿真验证
Multifunction digital clock, to achieve the timing, the school points, alarm clock, calendar and other functions, has been verified by simulation (2011-09-23, VHDL, 1251KB, 下载10次)
实现超多功能数字钟的vhdl硬件实现，可以实现校时校分闹铃，多模切换，多模同时工作
Ultra-versatile digital clock vhdl hardware implementation can be achieved when the school hours the school alarm, multi-mode switching, multi-mode simultaneously (2011-08-03, VHDL, 519KB, 下载4次)
1.计时功能：包括时、分、秒的计时
2.定时与闹钟功能：能在设定的时间按发出闹铃声
3.校时功能：对小时、分钟和秒能手动调整以校准时间
4.整点报时功能
5.利用数码管显示时间
1. The timer function: including, minutes and seconds when the timing
2. The timing and alarm clock function: set time out according to the alarm
3. When the function of hours, minutes and: can manual adjustments to calibration second time
4. Strike on the function
5. Using digital pipe display time (2011-07-29, VHDL, 2KB, 下载4次)
用Verilog编写的数字钟与汽车尾灯模块。其中数字钟具有时间显示的基本功能，按键校时校分，闹钟模块（包含校时校分），仿电台报时（四低一高），整点报时，12-24显示切换等强大功能。
With a digital clock in Verilog modules and automotive taillights. Digital clock which displays the basic functions of a time, school hours when school keys, alarm clock module (including school hours at school), imitation radio repeater (four low-high), the whole point timekeeping ,12-24 shows switching power. (2011-06-26, Others, 235KB, 下载3次)
用VHDL编写。数字钟校时电路，根据表示是否校时的输入引脚、是校正小时还是校正分钟的输入引脚决定校正状态。接受一个按钮的脉冲输入，每输入一个脉冲，被校正的时间增加1.与我的其它8个模块配套构成一个数字钟。
Programmed with VHDL.The time-revising circuit of a digital clock. Detect the inputs and decide if revise time, hour or minute. It recepts an impulse input from a key and the currently revised time will increase by 1 for each pushing of the key. (2011-06-24, VHDL, 116KB, 下载4次)
用VHDL编写。称为校时闪烁电路。一般的电子表在校时时都会使被校正的时间不停地闪烁。此模块实现了类似的功能。与我的其它8个模块配套构成一个数字钟。
Programmed with VHDL. It is called a flashing circuit(when time is being revised).Generally, a digital watch will flash the currently revised time(for example,hour) to let the user know time revised. This module implements the similar function. It is one of my total 9 modules that are used to design a digital clock. (2011-06-24, VHDL, 140KB, 下载4次)
① 用EDA实训仪的I/O设备和PLD芯片实现数字日历的设计。
② 数字日历能够显示年、月、日、时、分和秒。
③ 用EDA实训仪上的8只八段数码管分两屏分别显示年、月、日和时、分、秒，即在一定时间段内显示年、月、日（如20080101），然后在另一时间段内显示时、分、秒（如00123625），两个时间段能自动倒换。
④ 数字日历具有复位和校准年、月、日、时、分、秒的按钮，但校年和校时同用一个按钮，即在显示年、月、日时用此按钮校年，在显示时、分、秒时则用此按钮校时，依此类推。
① The EDA training instrument I/O devices and PLD chip digital calendar design.
② Figures calendar can display year, month, day, hours, minutes and seconds.
③ instrument training with EDA eight out of eight two-screen digital display, respectively, year, month, day and hour, minute, second, that a certain period of time shows year, month, day (eg 20080101), then another period of time shows hours, minutes, seconds (eg, 00123625), automatically switching the two time periods.
④ reset and calibrated with a digital calendar year, month, day, hour, minute, second button, but when the school year and school with a button that displays the year, month, day use this button when the school year, when the display , minutes, seconds, use this button to school, and so on.
(2011-06-22, Others, 4878KB, 下载12次)
数字钟的实现，包括报时，校时，清零，闹钟等功能，内附源文件电路图跟源代码。
This is a digital clock to achieve the VHDL. Using eight digital tube display!- Adjustable alarm can be school. (2011-06-15, VHDL, 90KB, 下载4次)
利用QuartusII7.0、MATLAB以及SmartSOPC实验系统进行多功能数字钟的设计是本次试验的主要内容。该数字中需包含的功能主要有：分频、校时校分、清零、动态显示、整点报时、闹钟闹铃、秒表以及24小时制和12小时制的转换等。
QuartusII7.0, MATLAB, and SmartSOPC experimental system for the design of multi-function digital clock is the main content of the trial. The figure is included in the functions needed are: sub-band, school, when school hours, resetting, dynamic display, the whole point timekeeping, alarm clock alarm, stopwatch and 24-hour system and 12-hour system conversion. (2011-06-08, VHDL, 249KB, 下载9次)