(1)设计一个具有‘时’、‘分’、‘秒’的十进制数字显示（小时从00～23）计时器。
(2)具有手动校时、校分的功能。
(3)闹钟功能，能在设定的时间发出提醒（绿色LED灯闪烁）。
(4)能进行整点报时。从59分50秒起，每隔2秒钟绿色LED灯闪一次，连续5次，达到整点时红色LED灯闪一次。
(1) design a ' when' , ' points' , ' s' decimal digital display (hour timer from 00 to 23). (2) having a manual correction, the correction sub functions. (3) The alarm clock function, can send reminders at a set time (green LED flashes). (4) The whole point timekeeping. Starting at 59 minutes and 50 seconds, every 2 seconds the green LED lights flash five times in a row, when the whole point of the red LED lights flash once. (2013-03-27, VHDL, 2KB, 下载3次)
DE2平台上实现的数字钟，包含时、分、秒的24小时制时间系统，有校时，准点报时，整点广播等功能。
DE2 platform digital clock, contains, minutes, seconds, 24-hour time system, school, prospective point of time, the whole point of broadcasting. (2013-01-05, Others, 1111KB, 下载5次)
简单的电子钟 实现时分秒，校时，定时，闹钟功能
Electronic clock (hour, minute, and second, the school, the timing, alarm clock) (2012-12-31, Visual C++, 341KB, 下载2次)
数字钟verilog程序，实现了校时、闹钟校正、整点报时、当前时间与闹钟时间切换显示功能。
Digital clock verilog program, school, alarm clock correction, the whole point timekeeping function. (2012-12-15, VHDL, 100KB, 下载10次)
数字电路时间以12小时为一个周期，显示时、分、秒，具有校时功能，可以分别对时及分进行单独校时，使其校正到标准
时间计时过程具有报时功能，当时间到达整点前10秒进行蜂鸣报时
SHUZISHIZHONG (2012-12-10, MultiPlatform, 3873KB, 下载10次)
多功能时钟，具有正常显示，校时，整点报时，闹钟功能。
Multi-function clock, with a normal school, the whole point timekeeping, alarm clock function. (2012-11-26, VHDL, 470KB, 下载5次)
数字钟(for DE2 开发板)
1.‘时’、‘分’、‘秒’的十进制数字显示（小时从00～23）计时器。
2. 手动校时、校分、校秒的功能。
3．定时与闹钟功能，能在设定的时间发出闹铃声。
4．进行整点报时。从59分50秒起，每隔2秒钟发出一次低音“嘟”的信号，连续5次，最后一次发出高音“嘀”的信号，此信号结束即达到整点。
5、一个秒表，最低位1 秒、60秒，手动停止，手动重置。
6、一个倒计时，显示小时、分钟、秒，可设置时间。
Decimal digital display (hour digital clock (for DE2 development board). ' ' , ' Minutes' , ' seconds' timer from 00 to 23). 2 when manually school, the school points School sec functionality. 3. Timer and alarm clock function, the alarm sounds at the set time. 4. The whole point of time. Starting at 59 minutes and 50 seconds, every 2 seconds issued time bass " beep" signal, five times in a row, the last issued a the treble " tick" signal, this signal the end to reach the whole point. 5, a stopwatch, the lowest 1 seconds, 60 seconds, manually stop manually reset. 6, a countdown display hours, minutes, seconds, set the time. (2012-11-11, VHDL, 887KB, 下载77次)
数字时钟，可以实现(1) 显示日期功能（年、月、日、时、分、秒以及）
(2) 可通过按键切换年、月、日及时、分、秒的显示状态
(3) 可随时调校年、月、日或时、分、秒
(4) 可每次增减一进行时间调节
(5) 可动态完整显示年份，实现真正的万年历显示
(6) 可显示温度
Digital clock, can be achieved (1) the date function (year, month, day, hour, minute, seconds as well) (2) through the key switch the year, month, day in a timely manner, minute, second display state (3) at any time adjust the year, month, day or time, minutes, seconds (4) can be added or deleted, a time adjustment (5) can be dynamically complete display Year, the real calendar display (6) to display temperature (2012-10-15, Others, 231KB, 下载6次)
vhdl数字钟，有校时校分整点报时的基本功能
vhdl digital clock school, the school divided the whole point timekeeping function (2012-09-19, VHDL, 256KB, 下载30次)
数字钟设计 计时计数器用24进制计时电路；
可手动校时，能分别进行时、分的校正；
整点报时；
选做：可设置闹时功能，当计时计到预定时间时，扬声器发出闹铃信号，闹铃时间为4s，并可提前终止闹铃。
Digital clock design (2012-09-03, VHDL, 709KB, 下载7次)
利用8051单片机写的数字钟程序，显示采用了数码管，有校时的功能。
Digital clock written in 8051, showing the digital control, and school functions. (2012-08-01, C/C++, 25690KB, 下载4次)
电子表的设计包括正常计时模块，LED显示模块，定时报警模块，校时模块，秒表模块
module clock(clk,rst,clock_en,second,minute,hour)
input clk,rst,clock_en
output[5:0]second,minute,hour
reg[5:0]second,minute,hour
(2012-06-19, VHDL, 109KB, 下载3次)
本数字钟可实现正常计时，支持12小时和24小时两种计时方式的切换，允许用户手动调时和整点报时功能。
系统对外向用户提供了两个按键:功能键和调整键.功能键用于功能选择,调整键用于相关的时间调整. 当接通电源后系统便开始正常计时，如果按一下功能键，则进入调小时模式,再按一次则进入调分模式,再按则进入12/24小时模式选择设定,再按则恢复到正常计时状态. 在正常计时状态下，用户可以选择12或24小时的计时方式，第六个数码管的右下方小点亮表示是12小时模式，不亮表示24小时。整点报时时，六个数码管的小点会同时亮。
当用户通过按键进入校时状态时，第二个数码管的小点变亮，表示现在在对小时进行设置；同样，进行校分状态时，第四个数码管的小点会亮，表示现在正在对分钟进行设置。
The digital clock can achieve normal timing, support for 12 hours and 24 hours two timing mode switch allows the user to manually tune and the whole hour. Systems external to provide users with two keys: the function key and adjust the key function keys for function selection and adjustment button for the relevant time to adjust the power system began timing, if you click a function key, adjust the hour mode, and then once for the tone patterns, and then enter 12/24 hour mode select Settings, and then restored to normal timekeeping. in normal time status, the user can select 12 or 24 hours timing sixth of the way, the bottom right of the small digital tube light 12 hour mode, light 24 hours. The whole point of time when the dot of six digital tube light. Button to enter the school when the second digital tube light, that now the hour set Similarly, when the school sub-state, the fourth digital control points will be bright, said that now are minute set. (2012-05-25, VHDL, 17KB, 下载3次)
基于UP3borad开发板的时钟设计，可校时，设置闹钟等
Clock design based on UP3borad the development board, can the school, set the alarm (2012-05-23, VHDL, 354KB, 下载6次)
用verilog编写的闹钟程序，含闹钟设置，计时，校时模块。
With verilog write alarm clock program, including alarm, timing, when the module. (2012-05-17, Others, 392KB, 下载6次)
基于FPGA的多功能数字钟系统（层次化设计）拓展功能包括：报时、校时校分、6到18点时段控制亮灯
Multi-functional digital clock system (hierarchical design) in the FPGA-based development features include: timekeeping, school Calibration of 6-18 hours to control lighting
(2012-05-17, VHDL, 560KB, 下载7次)
用方波信号发生器发出1HZ的稳定的方波信号作为CP信号输入 ,秒计数器满60向分计数器进位,分计数器满60向小时进位,小时计数器按“23翻0”规律计数，计数器经译码器送到显示器；计数出现误差可用校时电路进行校时、校分、校秒。并具有可整点报时与定时闹钟的功能。
本数字钟的功能列表如下：
1）基本功能：秒、分钟、小时计时、显示及校对；
2）整点报时功能：在每小时59分50秒开始500Hz频率发声提示，整点时1000Hz发声，之后声音停止；
3）定时报闹功能：可设定闹钟定点报闹，可用开关关闭；
Square wave signal generator with a 1 HZ stability of square wave signal as CP signal input, counter full 60 seconds to points counter carry and points to counter full 60 hours carry and hours counter press "23 turn 0" rule count, the counter decoder to display Count serious error when the circuit can be used when the school, the school to points, the school to seconds. And has the time and timing of the alarm clock function.
The function of the digital clock listed below:
1) the basic function: seconds, minutes, hours timer, display and proofreading
2) hourly chime function: every hour on 59 points 50 seconds began to 500 Hz frequency voice prompt, the hour 1000 Hz uttered his voice, the voice after stop
3) set times make function: to set the alarm clock fixed-point report make, can be used to switch to shut down
(2012-03-20, Others, 675KB, 下载6次)
本设计主要研究基于FPGA的数字钟，要求时间以24小时为一个周期,显示年、月、日、时、分、秒。具有校时以及报时功能，可以对年、月、日、时、分及秒进行单独校对，使其校正到标准时间。
This design is the main research based on FPGA digital clock, required time to 24 hours for a cycle, display date and time, minutes and seconds. The strike has and function, can to year, month, day, and minutes and seconds to the separate proofreading (2012-03-18, VHDL, 157KB, 下载4次)
clk： 标准时钟信号，本例中，其频率为4Hz；
clk_1k： 产生闹铃音、报时音的时钟信号，本例中其频率为1024Hz；
mode： 功能控制信号；为0：计时功能；
为1：闹钟功能；
为2：手动校时功能；
turn： 接按键，在手动校时功能时，选择是调整小时，还是分钟；
若长时间按住该键，还可使秒信号清零，用于精确调时；
change： 接按键，手动调整时，每按一次，计数器加1；
如果长按，则连续快速加1，用于快速调时和定时；
hour,min,sec ：此三信号分别输出并显示时、分、秒信号，
皆采用BCD码计数，分别驱动6个数码管显示时间；
alert： 输出到扬声器的信号，用于产生闹铃音和报时音；
闹铃音为持续20秒的急促的"嘀嘀嘀"音，若按住"change"键，
则可屏蔽该音；整点报时音为"嘀嘀嘀嘀-嘟"四短一长音；
LD_alert： 接发光二极管，指示是否设置了闹钟功能；
LD_hour： 接发光二极管，指示当前调整的是小时信号；
LD_min： 接发光二极管，指示当前调整的是分钟信号。
clk: standard clock signal, in this case, the frequency of 4Hz
clk_1k: generate the alarm sound, chime sound clock signal, in this case the frequency of 1024Hz
mode: Functional control signal 0: Chronograph function
1: The alarm clock function
2: Manually school-time functionality
turn: access keys manually school function, the choice is to adjust hours or minutes
If you long press the key, also make clear of the second signal for precise tone
change: access key, and manually adjust each time you press the counter plus 1
If long, then in quick succession plus one for fast tune and timing
hour, min, sec: This signal is output and display hours, minutes and seconds signal,
All use a BCD count, drive six digital display time
alert: Output signal to the speaker used to generate the alarm tone chime sound
The alarm tone for the last 20 seconds of rapid beeping beep "tone, if hold down the" change "button,
Can be shielded from the sound the whole point timekeeping w (2012-03-05, Windows_Unix, 480KB, 下载4次)
基于FPGA的数字时钟，能校时、校分，整点报时。
fpga clock (2012-03-02, VHDL, 316KB, 下载12次)