在Nexys A7 FPGA板上使用VHDL设计并实现了智能停车系统。
Design and implement a smart parking system using VHDL on the Nexys A7 FPGA board. (2024-03-21, VHDL, 0KB, 下载0次)
存储NEXYS A7（包括微处理器）的所有代码的存储库。主要在VHDL中。
Repository that holds all code for NEXYS A7, including for the microprocessor. Mostly in VHDL. (2024-03-09, VHDL, 0KB, 下载0次)
在Arty A7 FPGA上开发的音效项目。
Sound Effects Project developed on Arty A7 FPGA. (2024-02-27, VHDL, 0KB, 下载0次)
Arty A7 100T FPGA开发板上的SoomRV
SoomRV on the Arty A7 100T FPGA dev board (2023-11-22, VHDL, 0KB, 下载0次)
这是我使用Digilent.的ARTY A7 35T开发板实现的采样器。，
This is my implementation of a Sampler using the ARTY A7 35T developement board by Digilent., (2022-04-15, VHDL, 0KB, 下载0次)
97-98第一学期VLSI，Jahanian博士，
97-98 first semester VLSI by Dr. Jahanian, (2019-01-01, VHDL, 0KB, 下载0次)
GRLIB GPL支持Digilent CMOD A7 35T板
GRLIB GPL support for Digilent CMOD A7 35T board (2020-01-05, VHDL, 2651KB, 下载0次)
一种基于MRISC32-A1 CPU的计算机（FPGA SoC）
A computer (FPGA SoC) based on the MRISC32-A1 CPU (2023-03-30, VHDL, 385KB, 下载0次)
useful demo peoject using cmod a7
useful demo peoject using cmod a7 (2018-12-15, VHDL, 247KB, 下载0次)
modulemajority (major, V1, V2, V3)
start your comments with a forward slash and star and finish it with a star and forward slash.
output major
inputV1, V2, V3
wireN1, N2, N3
and A0 (N1, V1, V2)
andA1 (N2, V2, V3)
and A2 (N3, V3, V1)
orOr0(major, N1, N2, N3)
// Use two forward slashes for one line comments
Endmodule Each line of text in Verilog must terminate with a semicolon except endmodule.
modulemajority (major, V1, V2, V3)
start your comments with a forward slash and star and finish it with a star and forward slash.
output major
inputV1, V2, V3
wireN1, N2, N3
and A0 (N1, V1, V2)
andA1 (N2, V2, V3)
and A2 (N3, V3, V1)
orOr0(major, N1, N2, N3)
// Use two forward slashes for one line comments
Endmodule Each line of text in Verilog must terminate with a semicolon except endmodule. (2014-11-08, VHDL, 125KB, 下载1次)
--a0 a1 的输入我们用 k1 k2 代替
--b0 b1 的输入我们用 k3 k4 代替
--一开始数码管显示的是9.应为(11)*(11)就等于9
--数码管显示相减结?
- A0 a1 input we use the k1 k2 instead- b0 b1 input with k3 k4 instead- a digital display is 9. (11)* (11) is equivalent to 9- digital display subtracting the knot? (2013-04-03, VHDL, 1KB, 下载2次)
--a0 a1 a2的输入我们用 k1 k2 k3 代替
--b0 b1 b2的输入我们用拨码开关代替。
--b0用拨码开关1输入，BMK1用杜邦线接24脚
--b1用拨码开关2输入，BMK2用杜邦线接25脚
--b2用拨码开关3输入，BMK3用杜邦线接26脚
--一开始数码管显示的是0.应为111-111就等于0
--数码管显示相减结果
- A0 a1 a2 input we use k1 k2 k3 instead the- b0 b1 b2 input, we use DIP switches instead.- B0 DIP switch input, BMK1 with DuPont line by 24 feet- b1 DIP switch 2 input, BMK2 with DuPont line by 25 feet- b2 DIP switch 3 input, BMK3 connected with DuPont line 26 feet- a digital display of 0 is equivalent to 111-111 0- digital display subtraction results (2013-04-03, VHDL, 1KB, 下载2次)
--a0 a1 a2的输入我们用 k1 k2 k3 代替
--b0 b1 b2的输入我们用拨码开关代替。
--b0用拨码开关1输入，BMK1用杜邦线接24脚
--b1用拨码开关2输入，BMK2用杜邦线接25脚
--b2用拨码开关3输入，BMK3用杜邦线接26脚
--所以一开始数码管显示的是E.应为111加111就等于E(14)
--数码管显示相加结果
- A0 a1 a2 input we use k1 k2 k3 instead the- b0 b1 b2 input, we use DIP switches instead.- B0 DIP switch input, BMK1 with DuPont line by 24 feet- b1 DIP switch 2 input, BMK2 with DuPont line by 25 feet- b2 DIP switch 3 input, BMK3 connected with DuPont line 26 feet- beginning digital tube display E. should be 111 plus 111 is equal to E (14)- Digital tube display result of the addition (2013-04-03, VHDL, 1KB, 下载2次)
利用K1,K2来代替A2 A1 的数据输入。
利用K3,K4来代替B2 B1 的数据输入。
我把A0和B0都设置成1了。
所以一开始数码管显示的是E.应为111加111就等于E
数码管显示相加结果
K1, K2 to replace A2 A1 data input. K3, K4 to replace B2 B1 data input. A0 and B0 are set to 1. So beginning digital display E. should be 111 plus 111 is equal to the sum of the results of E digital display (2012-09-29, VHDL, 319KB, 下载3次)
4位并行加法器，a3,a2,a1,a0,b3,b2,b1,b0,cin为输入，cout,s3,s2,s1,s0为输出
4-bit parallel adder, a3, a2, a1, a0, b3, b2, b1, b0, cin as the input, cout, s3, s2, s1, s0 as the output (2010-07-13, VHDL, 1KB, 下载3次)
本实验箱采用的液晶显示屏内置的控制器为SED1520，点阵为122×32，需要两片SED1520组成，由E1，E2分别选通，以控制显示屏的左右两半屏。图形液晶显示模块有两种连接方式，一种为直接访问方式，一种为间接访问方式。本实验采用直接控制方式。
直接控制方式就是将液晶显示模块的接口作为存储器或I/O设备直接挂在计算机总线上。计算机通过地址译码器控制E1和E2的选通；读/写操作信号R/W有地址线A1
控制，命令/数据寄存器选择信号由地址线A0控制。
The experimental box with built-in LCD controller for the SED1520, lattice is 122 × 32, needs two SED1520 formed by the E1, E2, respectively gating to control the display of about two and a half screen. Graphic LCD module has two connections, one for the direct access method, an indirect access. In this study the direct control mode. Direct control method is to interface LCD module as memory or I/O devices directly linked to the computer bus. Computer controlled by address decoder strobe E1 and E2 read/write signal R/W control the address lines A1, command/data register select control signal from the address line A0. (2010-04-07, VHDL, 1178KB, 下载9次)
ac`97 controller verilog codes
ac `97 controller verilog codes (2009-07-01, VHDL, 16KB, 下载6次)
his design is a comparator that compares consecutive bits a0...a3 with b0...b3
his design is a comparator that compares consecutive bits a0...a3 with b0...b3 (2009-04-08, VHDL, 45KB, 下载2次)
该模块的工作原理是把来自并行输入与状态控制模块的两组并行输出信号进行高低为对应的电平比较。
若对应状态相同则输出为1，否则为0。图中A0-A9为A组并行码；clk0为时钟信号，z为比较输出。
The module is the working principle is to parallel input from state control module with two sets of parallel output signals corresponding to high and low level for comparison. If the corresponding state of the same output as one, otherwise to 0. Map A0-A9 parallel code for the A group clk0 for the clock signal, z In order to compare the output. (2008-03-24, VHDL, 255KB, 下载4次)
本工程实现的是9位义位与串并变换模块
具体工作过程是：
在时钟CLK的上升沿触发下，从inp端输入接收m序列，按顺序inp->A9->A8->...->A0进行意味，同时把A9，A8，...A0的输出分别给B9，B8，B7,...从而完成串并转换的功能。Q端的信号取自A0的输出短，作为一位4位后的串行m序列信号。
clk为输入时钟信号；inp为接收序列信号输入；Q为串行序列输出；B0~B3为四位并行序列输出。
Realize this project is 9 Sememe transform module with the string and the specific work process is: In the rising edge of CLK clock trigger from inp input receiver m sequence, according to the order of inp- (2008-03-24, VHDL, 242KB, 下载18次)