合肥工业大学合肥校区(HFUT)计算机科学与技术专业(CS)。本仓库存有大一至大三的实验+课设及其源码,有疑问可以邮箱联系(回复时间不一定)。欢迎Star,会不定时更新
Computer Science and Technology (CS) at Hefei Campus of Hefei University of Technology (HFUT). This warehouse has the experiment+curriculum and its source code from freshman to junior. If you have any questions, you can contact us by email (the reply time is uncertain). Welcome Star, it will be updated irregularly (2024-01-21, Rich Text Format, 0KB, 下载0次)
数字钟的设计，系统分为5个模块，Freq_div模块，Clock_cnt模块，Clock_ctl模块，Key_ctl模块和Display模块。系统目标：用8个LED 显示时间，如9点25分10秒显示为，09－25－10。（2）设置2个按键，按键SET用于工作模式选择，按键UP用于校时。
Digital clock design, the system is divided into five modules, Freq_div module, Clock_cnt module, Clock_ctl module, Key_ctl module and Display Module. System goal: 8 LED display time as 9:25:10 displayed as ,09-25-10. (2) Set two buttons SET button for mode selection button when UP for school. (2014-03-28, Others, 1561KB, 下载2次)
基于QuartusII开发环境，Cyclone III开发板的VerilogHDL多功能数字钟程序。可实现24小时计时，手动校时，闹钟，整点报时功能。分频模块在仿真和烧写是需要改变。
QuartusII based development environment, Cyclone III development board VerilogHDL multifunction digital clock procedures. Can achieve 24-hour clock, manual timing, alarm, hourly chime functions. Frequency module in the simulation and programming needs to change. (2013-07-24, VHDL, 1895KB, 下载4次)
数字时钟6位数码管显示。主要器件为74ls48和74ls160 /74ls161。功能：1.显示时、分、秒。2. 可以24小时制或12小时制。3. 具有校时功能
Digital clock six digital tube display. Main components of 74ls48 and 74ls160/74ls161. Features: 1. Shows hours, minutes, seconds. (2) a 24-hour or 12-hour clock. 3 a school function (2013-07-18, Others, 490KB, 下载7次)
设计一台能显示时、分、秒的数字电子钟，具体要求如下：
（1）时计数器用24进制计时电路，分、秒计数器用60进制计分、计秒电路；
（2）可手动校时，能分别进行时、分的校正；
（3）能实现整点报时功能。
Design a table can display hours, minutes and seconds of digital electronic clock, the specific requirements are as follows: (a) when the counter with 24 hexadecimal timing circuits, minutes, seconds counter with 60 decimal points, namely, second circuit (2) may be Manually school, be able to separate hours, minutes correction (3) to achieve the whole point timekeeping function. (2013-06-23, VHDL, 913KB, 下载3次)
用 Verilog HDL 设计一个多功能数字钟，包含以下主要功能：
1） 计时，时间以 24 小时制显示；
2） 校时；
3） 闹钟：设定闹钟时间，可利用 LED 闪烁作为闹钟提示；
4） 跑表：启动、停止；
5） 其他。
Using Verilog HDL design a multi-functional digital clock contains the following main functions: 1) time, the time is displayed in 24-hour clock 2) school 3) Alarm Clock: Set the alarm time, you can use the LED flashes as an alarm 4) Stopwatch: start, stop 5) Other. (2013-04-24, VHDL, 1206KB, 下载33次)
(1)设计一个具有‘时’、‘分’、‘秒’的十进制数字显示（小时从00～23）计时器。
(2)具有手动校时、校分的功能。
(3)闹钟功能，能在设定的时间发出提醒（绿色LED灯闪烁）。
(4)能进行整点报时。从59分50秒起，每隔2秒钟绿色LED灯闪一次，连续5次，达到整点时红色LED灯闪一次。
(1) design a ' when' , ' points' , ' s' decimal digital display (hour timer from 00 to 23). (2) having a manual correction, the correction sub functions. (3) The alarm clock function, can send reminders at a set time (green LED flashes). (4) The whole point timekeeping. Starting at 59 minutes and 50 seconds, every 2 seconds the green LED lights flash five times in a row, when the whole point of the red LED lights flash once. (2013-03-27, VHDL, 2KB, 下载3次)
数字钟(for DE2 开发板)
1.‘时’、‘分’、‘秒’的十进制数字显示（小时从00～23）计时器。
2. 手动校时、校分、校秒的功能。
3．定时与闹钟功能，能在设定的时间发出闹铃声。
4．进行整点报时。从59分50秒起，每隔2秒钟发出一次低音“嘟”的信号，连续5次，最后一次发出高音“嘀”的信号，此信号结束即达到整点。
5、一个秒表，最低位1 秒、60秒，手动停止，手动重置。
6、一个倒计时，显示小时、分钟、秒，可设置时间。
Decimal digital display (hour digital clock (for DE2 development board). ' ' , ' Minutes' , ' seconds' timer from 00 to 23). 2 when manually school, the school points School sec functionality. 3. Timer and alarm clock function, the alarm sounds at the set time. 4. The whole point of time. Starting at 59 minutes and 50 seconds, every 2 seconds issued time bass " beep" signal, five times in a row, the last issued a the treble " tick" signal, this signal the end to reach the whole point. 5, a stopwatch, the lowest 1 seconds, 60 seconds, manually stop manually reset. 6, a countdown display hours, minutes, seconds, set the time. (2012-11-11, VHDL, 887KB, 下载77次)
本设计主要研究基于FPGA的数字钟，要求时间以24小时为一个周期,显示年、月、日、时、分、秒。具有校时以及报时功能，可以对年、月、日、时、分及秒进行单独校对，使其校正到标准时间。
This design is the main research based on FPGA digital clock, required time to 24 hours for a cycle, display date and time, minutes and seconds. The strike has and function, can to year, month, day, and minutes and seconds to the separate proofreading (2012-03-18, VHDL, 157KB, 下载4次)
1.计时功能：包括时、分、秒的计时
2.定时与闹钟功能：能在设定的时间按发出闹铃声
3.校时功能：对小时、分钟和秒能手动调整以校准时间
4.整点报时功能
5.利用数码管显示时间
1. The timer function: including, minutes and seconds when the timing
2. The timing and alarm clock function: set time out according to the alarm
3. When the function of hours, minutes and: can manual adjustments to calibration second time
4. Strike on the function
5. Using digital pipe display time (2011-07-29, VHDL, 2KB, 下载4次)
用VHDL编写。称为校时闪烁电路。一般的电子表在校时时都会使被校正的时间不停地闪烁。此模块实现了类似的功能。与我的其它8个模块配套构成一个数字钟。
Programmed with VHDL. It is called a flashing circuit(when time is being revised).Generally, a digital watch will flash the currently revised time(for example,hour) to let the user know time revised. This module implements the similar function. It is one of my total 9 modules that are used to design a digital clock. (2011-06-24, VHDL, 140KB, 下载4次)
实验利借助于Quartus II 软件设计了一个多功能数字钟，实现了校时，校分，清零，保持和整点报时等多种基本功能，此外还实现了闹钟，星期，音乐闹铃等附加功能。本文首先利用Quartus II进行原理图设计并仿真调试，最后在实验板上验证了设计的正确性。
关键字：数字钟 闹钟 仿真 准点报时
Quartus II software by means of experimental Lee designed a multi-functional digital clock and realized the school, the school hours, cleared, and the whole point of time keeping and other basic functions, in addition to achieve the alarm clock, week, music, alarm, etc. Additional function. This paper carried out using Quartus II schematic design and simulation debugging, and finally verified in the experimental board design is correct. Keywords: digital clock alarm clock simulation of quasi-point of time (2010-05-08, VHDL, 1158KB, 下载13次)
基于FPGA的数字电子钟设计，系统总程序由分频模块、“时分秒”计数器模块、数据选择模块、报时模块、动态扫描显示和译码模块组成。得到一个将“时”、“分”、“秒”显示于人的视觉器官的计时装置。它的计时周期为24小时，显示满刻度为23时59分59秒，另外有校时、校分和整点报时功能，并通过数码管驱动电路显示计时结果。
FPGA-based design of digital electronic clock, the system program by the total frequency module, " the minutes and seconds" counter module, data selection module, timer module, dynamic scanning display and decoding module. Get a will " ," and " division" and " seconds" display on the human visual organ of the timing device. It' s time for the 24-hour period, indicating full scale as 23:59:59, and another school, the school hours and the whole hour, and through digital tube display driver circuit timing results. (2010-04-07, VHDL, 62KB, 下载27次)
VHDL数字钟设计程序
设计要求
基本要求：
1、24小时计数显示；
2、具有校时功能（时，分） ；
附加要求：
1、实现闹钟功能（定时，闹响）；
VHDL digital clock design process design requirements for the basic requirements: 1,24 hours count display 2, with a school function (hours, minutes) additional requirements: 1, the realization of an alarm clock function (timing, downtown ring) (2008-12-23, VHDL, 7KB, 下载129次)
ADC0809采样控制电路的实现ADC0809是CMOS的8位A/D转换器，片内有8路模拟开关，可控制8个模拟量中的一个进入转换器中，转换时间约100us。主要控制信号有，START是转换启动信号，高电平有效。ALE是3位通道选择地址（ADDC、ADDB、ADDA）信号的所存信号。当模拟量送至某一输入端（如IN1或IN2），由3位地址信号选择，而地址信号由ALE锁存。
ADC0809频 实 ADC0809CMOS8位A/D 转 片8 模 饪?兀 煽8模 械一 转 校 转 时 约 100us要藕校START 转 藕牛 叩 平效ALE3位 通 选ADDCADDBADDA藕诺藕拧模 某一 耍 IN1IN23位藕选 瘢 藕ALE file (2008-09-04, VHDL, 28KB, 下载38次)
学习使用FPGA做一些简单的编码器,RS(5,3)编码就是5个字符中有5-3=2两个校正字
Learning to use the FPGA to do a few simple encoders, RS (5,3) code is five characters in 5-3 = 2 has two correction words (2008-04-01, VHDL, 969KB, 下载136次)
VHDL数字钟
数字电子钟 此数字电子钟具有的功能包括： 1. 计时，时、分、秒显示； 2. 十二小时与二十四小时之间的转换； 3. 上下午显示； 4. 对时、分、秒的校时功能；
VHDL digital clock digital clock digital electronic clock with this function include: 1. Time, hours, minutes and seconds display 2. 12 hours and 24 hours between the conversion 3. On the afternoon show 4. hours, minutes and seconds of the school function (2007-11-14, PHP, 3KB, 下载135次)
基于Altera公司系列FPGA(Cyclone EP1C3T144C8)、Verilog HDL、MAX7219数码管显示芯片、4X4矩阵键盘、TDA2822功放芯片及扬声器等实现了《电子线路设计• 测试• 实验》课程中多功能数字钟实验所要求的所有功能和其它一些扩展功能。包括：基本功能——以数字形式显示时、分、秒的时间，小时计数器为同步24进制，可手动校时、校分；扩展功能——仿广播电台正点报时，任意时刻闹钟（选做），自动报整点时数（选做）；其它扩展功能——显示年月日（能处理大月小月，可手动任意设置年月日），秒表（包括开始、暂停和清零）。
based Altera FPGA series (Cyclone EP1C3T144C8) , Verilog HDL, MAX7219 Digital Display chips, 4x4 matrix keyboard, TDA2822 chip power amplifier and loudspeakers of the "Electronic Circuit Design (2007-04-17, Others, 23KB, 下载226次)
这是我电子线路测试的作业，在FPGA板上实现数字钟，（Max2环境）采用VHDL语言编写，非常适合初学者。具备24小时计时，校时，低高音整点报时，定时和多重功能选择的功能。
This is my test of electronic circuits operating at the FPGA board digital clock (Max2 Environment) using VHDL language, very suitable for beginners. 24-hour time, the school, the whole point of low Treble timekeeping, the timing and choice of multiple functional function. (2007-01-31, MultiPlatform, 495KB, 下载26次)
数字电子钟 此数字电子钟具有的功能包括： 1. 计时，时、分、秒显示； 2. 十二小时与二十四小时之间的转换； 3. 上下午显示； 4. 对时、分、秒的校时功能； 5. 跑表功能。
digital electronic clock this digital electronic clock with functions include : 1. Time, hours, minutes and seconds display; 2. 12 hours with 24 hours of conversion; 3. On the afternoon show; 4. Right hours, minutes, and seconds school function; 5. Stopwatch functions . (2005-05-09, WORD, 7KB, 下载351次)