程序是实现一个数字钟，有进位、清零、校时与校分功能。数字钟的分钟和小时是用数码管显示
COUNTER AND ALARMProblem C. Cave Escape Google Kickstart Round G 2018 [Small Input] (2019-04-26, Verilog, 1599KB, 下载1次)
12制 24制可切换电子钟，有时分秒，都可校时
clock can adjust minute,hour,seconds (2018-05-11, Verilog, 747KB, 下载1次)
基于verilog简单数字时钟程序，可实现校时，校分功能
Based verilog simple digital clock procedures, can be achieved when the school, school division function (2016-07-03, VHDL, 1128KB, 下载1次)
数字电路时间以12小时为一个周期，显示时、分、秒，具有校时功能，可以分别对时及分进行单独校时，使其校正到标准
时间计时过程具有报时功能，当时间到达整点前10秒进行蜂鸣报时
SHUZISHIZHONG (2012-12-10, MultiPlatform, 3873KB, 下载10次)
vhdl数字钟，有校时校分整点报时的基本功能
vhdl digital clock school, the school divided the whole point timekeeping function (2012-09-19, VHDL, 256KB, 下载30次)
数字钟设计 计时计数器用24进制计时电路；
可手动校时，能分别进行时、分的校正；
整点报时；
选做：可设置闹时功能，当计时计到预定时间时，扬声器发出闹铃信号，闹铃时间为4s，并可提前终止闹铃。
Digital clock design (2012-09-03, VHDL, 709KB, 下载7次)
基于FPGA的多功能数字钟系统（层次化设计）拓展功能包括：报时、校时校分、6到18点时段控制亮灯
Multi-functional digital clock system (hierarchical design) in the FPGA-based development features include: timekeeping, school Calibration of 6-18 hours to control lighting
(2012-05-17, VHDL, 560KB, 下载7次)
基于FPGA的数字时钟，能校时、校分，整点报时。
fpga clock (2012-03-02, VHDL, 316KB, 下载12次)
verilog写的时钟程序，带有校时和闹铃功能
clock program written with verilog (2012-02-25, VHDL, 2KB, 下载7次)
实现超多功能数字钟的vhdl硬件实现，可以实现校时校分闹铃，多模切换，多模同时工作
Ultra-versatile digital clock vhdl hardware implementation can be achieved when the school hours the school alarm, multi-mode switching, multi-mode simultaneously (2011-08-03, VHDL, 519KB, 下载4次)
用Verilog编写的数字钟与汽车尾灯模块。其中数字钟具有时间显示的基本功能，按键校时校分，闹钟模块（包含校时校分），仿电台报时（四低一高），整点报时，12-24显示切换等强大功能。
With a digital clock in Verilog modules and automotive taillights. Digital clock which displays the basic functions of a time, school hours when school keys, alarm clock module (including school hours at school), imitation radio repeater (four low-high), the whole point timekeeping ,12-24 shows switching power. (2011-06-26, Others, 235KB, 下载3次)
B码的产生 使用B码进行校时 用来产生B码
以及B码的格式 说明
B generated code when using the B codes school code used to generate B and B code format description (2010-07-23, VHDL, 332KB, 下载130次)
B码校时（B码的产生）用来产生B码，实现B码校时 使设备进行同步。
B码校时（B码的产生）用来产生B码，实现B码校时 使设备进行同步。 (2010-07-23, VHDL, 5KB, 下载89次)
电子钟（模式转换24/12进制，校时，校分）
Clock (24/12 hex mode conversion, school hours, school hours) (2010-07-09, VHDL, 102KB, 下载2次)
这时用VHDL语言编写的多功能数字钟，具有正常的计时功能，还能进行校时、校分，并且具有整点报时功能
Then with the VHDL language multi-functional digital clock, with the normal timing functions, but also to the school, the school hours, and have the whole point timekeeping function of (2009-09-22, VHDL, 445KB, 下载13次)
数字钟的VHDL源程序，可以实现校时，校分等功能，并在试验箱上运行成功
The VHDL source code digital clock, you can achieve at school, school grade features, and success in the chamber is running on (2009-04-08, VHDL, 302KB, 下载5次)
数字钟的VHDL源程序，可以实现校时，校分等功能，并在试验箱上运行成功
The VHDL source code digital clock, you can achieve at school, school grade features, and success in the chamber is running on (2009-04-08, VHDL, 303KB, 下载6次)
两个按键控制校时的VHDL时钟源码，带定时闹钟和日历功能
Two buttons control the school at the time of VHDL source clock, alarm clock and calendar with timing function (2008-07-11, VHDL, 2KB, 下载17次)
本程序为模拟可校时的时钟程序；clk--时钟信号,rst--清零信号,set_en--校时 使能信号,faster--快进信号,slower--快退信号,hour--小时校时,min--分钟校 时,（hh,hl,ml,mh,sh,sl）--时，分，秒显示信号。 校时的时候，秒清零。 (2008-05-02, VHDL, 110KB, 下载2次)
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使用Verilog语言编写的数字钟程序.有慢校时,快校时,闹钟等功能.
use Verilog language prepared by the digital clock procedures. Schools are slow, quick school, alarm clock functions. (2006-06-02, Unix_Linux, 5KB, 下载47次)