实现计时，置数，闹钟设置，切换显示等
1.硬件资源：FPGA开发板一块，电源线一根，下载器一个
2.开发板用到的资源：三颗独立按键，一位拨码开关，八位七段数码显示器，
蜂鸣器
3.功能设计：时钟功能，校时功能，闹钟功能
整个系统分为7大模块
Realize timing, setting, alarm setting, switching display, etc
1. Hardware resources: one FPGA development board, one power cord and one Downloader
2. Resources used in the development board: three independent buttons, one dial switch, eight seven segment digital display,
Buzzer
3. Function design: clock function, timing function, alarm function
The whole system is divided into seven modules (2020-06-16, Verilog, 2381KB, 下载0次)
信号定义： clk： 标准时钟信号，本例中，其频率为4Hz； clk_1k： 产生闹铃音、报时音的时钟信号，本例中其频率为1024Hz； mode： 功能控制信号； 为0：计时功能； 为1：闹钟功能； 为2：手动校时功能； turn： 接按键，在手动校时功能时，选择是调整小时，还是分钟； 若长时间按住该键，还可使秒信号清零，用于精确调时； change： 接按键，手动调整时，每按一次，计数器加1； 如果长按，则连续快速加1，用于快速调时和定时； hour,min,sec：此三信号分别输出并显示时、分、秒信号， 皆采用BCD码计数，分别驱动6个数码管显示时间； alert： 输出到扬声器的信号，用于产生闹铃音和报时音； 闹铃音为持续20秒的急促的“嘀嘀嘀”音，若按住“change”键， 则可屏蔽该音；整点报时音为“嘀嘀嘀嘀—嘟”四短一长音； LD_alert： 接发光二极管，指示是否设置了闹钟功能； LD_hour： 接发光二极管，指示当前调整的是小时信号； LD_min： 接发光二极管，指示当前调整的是分钟信号。
Signal definition: clk: standard clock signal, in this case, the frequency of 4Hz clk_1k: generating an alarm sound, the sound of the chime of the clock signal, in this case a frequency of 1024Hz mode: function control signal to 0: timing functions 1: alarm clock function 2: Manual calibration function turn: take the keys, function in the manual when school choice is to adjust the hours, or minutes if long press the button, but also to second signal cleared for precise time-setting change: access key, manually adjust the time, every time you press, the counter is incremented if long press, then in quick succession by 1, when used to quickly tune and timing hour, min, sec: The three signals are output and display hours, minutes, seconds signal using BCD code are counted separately driven six digital tube display time alert: a signal output to the speaker for generating an alarm tone chime tone alarm tone sustained 20 seconds of rapid " Didi tick" sound, if the hol (2015-12-09, VHDL, 16KB, 下载2次)
DLP Discovery 4100
数字微镜(DMD)空间光开关光调制器开发系统
1.全面兼容德州仪器TI DLP D4100 开发系统. 能够支持1920X1080 DMD(DMD微镜为10.6微米,本征分辨率为1920X1080)
数字微镜(DMD)空间光开关光调制器开发系统
2. 1024 X 768 的DMD(4:3)有两种微镜结构，一种是13.68 微米，
对角线长度为0.7 英寸；另一种是10.8 微米的，对角线长度为0.55
英寸；我们系统都能支持所有主流分辨率DMD
3. 支持USB2.0 高速度传输图片和控制信号
4. 开放式控制软件基于Windows XP 全速度USB驱动,在Visual
Basic 下编制,开发式接口, 易于高精度光学科研实验
5. 提供丰富的Windows XP 的USB 控制程序和API 开发系统
6. 支持XGA, 1080p 和1920x1200 分辨率单个微镜精确控制
7. 开放式FPGA 架构, 提供示例FPGA 的二次开发选择和客户
定制功能
8. 高速二进和任意灰度制图片显示 输入输出系统触发,支持通
用客户顶GPIO 口设置.
9. 我们能为客户提供全程独特定做和设计服务.
应用:
结构光投影,激光全息,无掩模光刻,高光谱成像,激光光束校形,
3D 测量和3D 打印机技术, 光谱分析.
Jefferson_zhao@163.com
DLP DMD Discovery 4100 (2014-01-20, Visual Basic, 6299KB, 下载31次)
数字时钟，可以实现(1) 显示日期功能（年、月、日、时、分、秒以及）
(2) 可通过按键切换年、月、日及时、分、秒的显示状态
(3) 可随时调校年、月、日或时、分、秒
(4) 可每次增减一进行时间调节
(5) 可动态完整显示年份，实现真正的万年历显示
(6) 可显示温度
Digital clock, can be achieved (1) the date function (year, month, day, hour, minute, seconds as well) (2) through the key switch the year, month, day in a timely manner, minute, second display state (3) at any time adjust the year, month, day or time, minutes, seconds (4) can be added or deleted, a time adjustment (5) can be dynamically complete display Year, the real calendar display (6) to display temperature (2012-10-15, Others, 231KB, 下载6次)
本数字钟可实现正常计时，支持12小时和24小时两种计时方式的切换，允许用户手动调时和整点报时功能。
系统对外向用户提供了两个按键:功能键和调整键.功能键用于功能选择,调整键用于相关的时间调整. 当接通电源后系统便开始正常计时，如果按一下功能键，则进入调小时模式,再按一次则进入调分模式,再按则进入12/24小时模式选择设定,再按则恢复到正常计时状态. 在正常计时状态下，用户可以选择12或24小时的计时方式，第六个数码管的右下方小点亮表示是12小时模式，不亮表示24小时。整点报时时，六个数码管的小点会同时亮。
当用户通过按键进入校时状态时，第二个数码管的小点变亮，表示现在在对小时进行设置；同样，进行校分状态时，第四个数码管的小点会亮，表示现在正在对分钟进行设置。
The digital clock can achieve normal timing, support for 12 hours and 24 hours two timing mode switch allows the user to manually tune and the whole hour. Systems external to provide users with two keys: the function key and adjust the key function keys for function selection and adjustment button for the relevant time to adjust the power system began timing, if you click a function key, adjust the hour mode, and then once for the tone patterns, and then enter 12/24 hour mode select Settings, and then restored to normal timekeeping. in normal time status, the user can select 12 or 24 hours timing sixth of the way, the bottom right of the small digital tube light 12 hour mode, light 24 hours. The whole point of time when the dot of six digital tube light. Button to enter the school when the second digital tube light, that now the hour set Similarly, when the school sub-state, the fourth digital control points will be bright, said that now are minute set. (2012-05-25, VHDL, 17KB, 下载3次)
clk： 标准时钟信号，本例中，其频率为4Hz；
clk_1k： 产生闹铃音、报时音的时钟信号，本例中其频率为1024Hz；
mode： 功能控制信号；为0：计时功能；
为1：闹钟功能；
为2：手动校时功能；
turn： 接按键，在手动校时功能时，选择是调整小时，还是分钟；
若长时间按住该键，还可使秒信号清零，用于精确调时；
change： 接按键，手动调整时，每按一次，计数器加1；
如果长按，则连续快速加1，用于快速调时和定时；
hour,min,sec ：此三信号分别输出并显示时、分、秒信号，
皆采用BCD码计数，分别驱动6个数码管显示时间；
alert： 输出到扬声器的信号，用于产生闹铃音和报时音；
闹铃音为持续20秒的急促的"嘀嘀嘀"音，若按住"change"键，
则可屏蔽该音；整点报时音为"嘀嘀嘀嘀-嘟"四短一长音；
LD_alert： 接发光二极管，指示是否设置了闹钟功能；
LD_hour： 接发光二极管，指示当前调整的是小时信号；
LD_min： 接发光二极管，指示当前调整的是分钟信号。
clk: standard clock signal, in this case, the frequency of 4Hz
clk_1k: generate the alarm sound, chime sound clock signal, in this case the frequency of 1024Hz
mode: Functional control signal 0: Chronograph function
1: The alarm clock function
2: Manually school-time functionality
turn: access keys manually school function, the choice is to adjust hours or minutes
If you long press the key, also make clear of the second signal for precise tone
change: access key, and manually adjust each time you press the counter plus 1
If long, then in quick succession plus one for fast tune and timing
hour, min, sec: This signal is output and display hours, minutes and seconds signal,
All use a BCD count, drive six digital display time
alert: Output signal to the speaker used to generate the alarm tone chime sound
The alarm tone for the last 20 seconds of rapid beeping beep "tone, if hold down the" change "button,
Can be shielded from the sound the whole point timekeeping w (2012-03-05, Windows_Unix, 480KB, 下载4次)
此数字钟具有时，分，秒计时并显示功能；
2.能进行24/12小时制计时模块的切换；
3.具有校时，清除功能，能对时，分，秒进行调整；
4.具有整点报时功能：在59分51秒，59分53秒，59分55秒，59分57秒发出低音256HZ信号，在59分59秒发出一次高音1024HZ信号，音响持续一秒钟，在1024HZ音响结束时刻即为整点；
This digital clock with hours, minutes, seconds, chronograph and display 2 24/12 hour time capable of switching modules 3 with the school, clean up, can the hours, minutes, seconds to adjust 4 with The whole point timekeeping functions: in 59 minutes and 51 seconds, 59 minutes and 53 seconds, 59 minutes and 55 seconds, 59 minutes and 57 seconds bass 256HZ signal sent in 59 minutes and 59 seconds to issue a treble 1024HZ signals, sound for one second, sound in 1024HZ end time is the whole point (2011-11-13, VHDL, 703KB, 下载4次)
电子钟的设计，(1) 计时功能：这是本计时器设计的基本功能，可进行时、分、秒计时，并显示。
(2) 闹钟功能：如果当前时间与设置的闹钟时间相同，则扬声器发出一段音乐，并维持一分钟。
(3) 调时调分调闹钟功能：当需要校时或者要重新设置闹钟的时间时，可通过实验箱上的按键控制。
The design of electronic clock, (1) timer function: This is the basic design of the timer function, can be hours, minutes, seconds, time, and displayed. (2) Alarm function: If the current time and set the alarm clock the same time, the speaker issued a piece of music, and to maintain a minute. (3) adjusting the tone when the tone alarm sub-functions: the school or when when you need to re-set the alarm time, the experimental box through the keys on the control. (2010-11-30, VHDL, 82KB, 下载7次)
VerilogHDL编译基本功能具有“秒”、“分”、“时”计时功能，小时按24小时制计时。具有校时功能，能对“分”和“小时”进行调整。扩展功能
仿广播电台正点报时。在59分51秒、53秒、55秒、57秒发出低音512Hz信号，在59分59秒时发出一次高音1024Hz信号，音响持续1秒钟，在1024Hz音响结束时刻为整点。
定时控制，其时间自定；
可任意设定时间的闹钟
自动报整点小时数
小时显示：可切换12小时/24小时显示
VerilogHDL compile the basic functions of a " second" , " division" and " when" time function, hour by 24-hour time. When a school function, can " divide" and " hours" to adjust. Radio extension punctual timekeeping imitation. In 59 minutes and 51 seconds, 53 seconds, 55 seconds, 57 seconds sent the bass 512Hz signal, in 59 minutes and 59 seconds to issue a Treble 1024Hz signal, sound for 1 second, the end of the 1024Hz sound time for the whole point. Timing control, its time to custom can be arbitrarily set the time automatically report the whole point of the alarm clock an hour for several hours show: switchable 12 hours/24 hours display (2010-06-20, VHDL, 1KB, 下载5次)
利用maxplus2完成
1、 完成带时、分、秒显示的24h计时功能；
2、 能完成整点报时功能，要求当数字钟的分和秒计数器计到59min52s时，驱动音响电路，四高一低，最后一声高声结束，整点时间到；
3、 完成对“时”和“分”的校时，并能对秒计数器清零。
Use maxplus2 completed one complete with hours, minutes, seconds, show 24h time functions 2, can complete the whole point timekeeping function, require that when the digital clock minutes, and seconds counter when the count to 59min52s, driver audio circuit, four high and one low, soon as the end of the last loud, the whole point of time to 3 to complete the " time" and " sub" when the school is also able to clear the seconds counter. (2009-11-01, WORD, 165KB, 下载7次)
数字钟的主要功能有年月日时分秒的显示输出功能和对日期及时间进行设置的功能，还可以有整点报时等功能。设计数字钟的核心问题是时钟日期的自动转换功能。即自动识别不同月份的天数的控制。据此可以设计一个如图１所示结构的数字钟，该数字钟包括校时模块、时分秒计时模块、年月日模块、和输出选择模块。
digital clock is the main function Minutes date when the output function and the date and time set for the function , they can point the entire timekeeping functions. Digital Clock Design is the core issue date of the clock automatic conversion function. Automatic identification is the number of days in the control. One can design a structure as shown in figure 1 of the digital clock, the digital clock module, including school, a time when every minute module, Date module, and choose the output module. (2007-04-16, Delphi, 372KB, 下载59次)